Eugene Leitl writes:
> This particular lunatic here thinks context switches need not
> be Nemesis, if the amount of context pushed can be minimized
> (hardware stack machines!), and if you use several copies of
> hardware which retain state, and only push around the one
> bit which flags the individual engines as currently active.
> Only doable as MISC, of course, where a CPU core is worth
> ~10 kTransistors.
SPARC, the MTA, and theoretically the new Alphas with SMT do this
already; none of them are MISC. If you have MISC, you can actually
have a bunch of concurrently-active engines on the same chip. The
difficulty then becomes this: what do you feed them?
-- <firstname.lastname@example.org> Kragen Sitaker <http://www.pobox.com/~kragen/> Perilous to all of us are the devices of an art deeper than we possess ourselves. -- Gandalf the White [J.R.R. Tolkien, "The Two Towers", Bk 3, Ch. XI]
This archive was generated by hypermail 2b29 : Fri Apr 27 2001 - 23:17:56 PDT