Kragen Sitaker wrote:
> SPARC, the MTA, and theoretically the new Alphas with SMT do this
> already; none of them are MISC. If you have MISC, you can actually
Yes, but I very much doubt these are $1 in quantities.
> have a bunch of concurrently-active engines on the same chip. The
> difficulty then becomes this: what do you feed them?
I dunno, if you can get ~kWord in few ns latency, and from SRAM
even faster this seems like a lot of memory bandwidth.
But, you won't be able to put up that many engines up there.
To start with, if your ALU is 1 kBit wide, you won't be
able to fit it into 10 kTransistors anymore. 100..200 kTransistors
for CPU plus networking, plus a few MTransistors for the memory,
and you have to keep the yield high, and thus the die inexpensive.
You would want to keep a second (possibly stripped) CPU, which
does OS and networking stuff without pushing around context bits,
but why having more? Rather make the thing smaller, and fit several
of them on a single die. Or use the whole wafer, as the networking
has enough redundancies so some 10-20 % of dead dies won't make a
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