From: Rohit Khare (Rohit@knownow.com)
Date: Mon Jun 19 2000 - 20:34:32 PDT
http://www.redherring.com/insider/2000/0615/tech-labrat061500.html
Lab Rat: Going clockless
By Phil Harvey
Redherring.com, June 15, 2000
It's tough for university-bred technology, no
matter how novel, to
grab the attention of the business community,
let alone the
general public. But take that same sleepy
technology and wrap a
youthful startup around it, and it won't be
long until the smell of
money awakens investors, the press, and the
man on the street.
That's what's happening to a tiny Pasadena,
California-based
startup called Asynchronous Digital Design
(ADD). The firm says
its technology -- based on a decade of
research from the
California Institute of Technology -- will
help it create a new kind
of high-performance microprocessor that
doesn't need a clock,
one of the required ingredients in most of
today's chips.
According to the company's founders, the
radical design could
produce semiconductors that have the same
performance level of
today's top chips, while consuming less
energy and having a
longer shelf life. Although the hurdle of
bringing such a product to
market is unprecedented, the growing need for
more low-power
microprocessors and a possible end of the
road for Moore's Law
makes ADD an idea worth considering.
Barely out of the dorm, ADD's attracted some
early funding from
the likes of Yobie Benjamin, Ernst & Young's
top strategist for its
e-commerce and emerging technology practice.
The firm has also
received investments from other individuals
who aren't quite as
chatty as Mr. Benjamin is during a recent
happy-hour meeting at
San Francisco's Mars Bar.
MOORE'S LAW VS. PHYSICS
In any case, ADD's development will be
interesting to watch in the
next few months because its technology and
timing seem to be
spot-on with the growing trend of computing
devices becoming
smaller and mobile, putting a premium on
speed and power
consumption.
Not many specific details about ADD's chip
are available yet. "We
don't want to talk about [the] processor
until we have some
silicon fabbed," says ADD President Uri Cummings. Mr.
Cummings, who founded the firm with Caltech
classmate Andrew
Lines, was nice enough, though, to help
explain why his firm's
asynchronous chip might someday be a big deal.
Since 1965, Moore's Law has always been an
easy measurement
of progress in the semiconductor industry. It
hails from Intel
(Nasdaq: INTC) co-founder Gordon Moore's
classic observation
that every 18 to 24 months, the number of
transistors on a chip,
and the chip's performance, will double.
For the most part, semiconductors have
evolved right along that
path. Today's chips are faster, and they use
more power than
their predecessors do. But the faster the
chips are, the tougher
and more expensive they are to design, build,
and maintain. And
because transistors give off more heat as
more are crowded onto
a chip, it's reasonable to assume that they
won't be able to
progress beyond certain physical limits.
CLOCKLESS CHIPS
So what happens in, say, the next 15 years,
when chips continue
shrinking and giving off heat -- do they
finally get as small and
as fast as they can get? Mr. Cummings and
other proponents of
asynchronous chip technology have an answer
on the tips of their
tongues: Try chips without clocks.
Most processors today are synchronous, meaning a clock
regulates their internal timing. Today we
measure how fast a
computer can execute instructions by the
number of clock cycles
per second. (A 300-MHz processor, like the
one in my PC, carries
out 300 million cycles per second.)
Unfortunately, clock-driven chips waste a lot
of the power they
consume by running in place. In muddier
language, each part of
the clock-governed processor operates in lock
step, meaning that
all stages in the processor's operation take
exactly as long as the
slowest stage. Instructions are passed from
each chip subsystem
to the next like cars on an assembly line.
ROCK AROUND THE CLOCK
Contrast that with asynchronous chips, where
the transistors can
theoretically switch independently of one
another and run at their
own speed. An asynchronous chip's subsystems can swap
information at mutually negotiated times,
without having to check
in with a clock. As a result, an asynchronous
chip exhibits the
power of its components' average performance.
A synchronous
chip, however, exhibits the performance of
its slowest component.
Also, an asynchronous chip also saves power
because it can shut
down parts of the circuit that aren't in use.
In other words, there's
no running in place.
Still, chip designers understand synchronous
chips better. Its
lock-step process seems a bit strange to
laymen, but its much
easier to visualize. PC Week's Peter Coffee
gave one of the best
illustrations of synchronous logic when he
wrote, "Imagine
working in an office where everyone picks up
the phone every 60
seconds to see if anyone is calling."
In turn, Byte Magazine's Dick Pountain,
described asynchronous
logic as a taxi service where cabs depart,
not at fixed times, but
only when they're carrying passengers.
Whatever you compare their craft with, Mr.
Lines and Mr.
Cummings are an interesting duo.
Theoretically, asynchronous
chips are the toughest kind to design. But
after years of studying
under Dr. Alain Martin, who developed and
"fabbed" the first
delay-insensitive, RISC-like asynchronous
processor in 1989,
these gentlemen say that asynchronous design
is the only kind
of circuit methodology they've been immersed in.
IN GOOD COMPANY
Naturally, they're not the only ones on Earth
studying this kind of
processor design. A good list of other firms
and universities
involved in this arena can be found at the
University of
Manchester's Web site.
The asynchronous backers seemed to be a
vibrant, somewhat
incestuous, technology community. As an
example, Dr. Ivan
Sutherland, a VP and Fellow at Sun Labs
(Nasdaq: SUNW), is well
known for his continuing work on asynchronous
processors. Mr.
Sutherland, who had lunch with the lads at
ADD earlier this week,
helped establish their field of study at
Caltech. It was during Dr.
Sutherland's teaching tenure at Caltech from
1976 to 1980 that
integrated circuit design became an
acceptable field of academic
study.
Mr. Lines and Mr. Cummings hope their lack of
legacy in the
synchronous chip world will help them create
an asynchronous
chip that's low-power, low-cost, and capable
of running complex
software programs. Although the commercial
uses for their
processor, called Vortex, haven't been fleshed out, Mr.
Cummings says the first chip fabbed by ADD will perform
comparably to a traditional 1-GHz processor.
At that speed,
potential uses for the low-power chip could
be as diverse as
mobile communications products, portable computers, and
networking gear.
Although ADD seems to be off to a flying
start, it has a long way
to go before it reaches commercial success.
As things stand now,
many of the problems previous asynchronous
designs addressed
are solved well enough with today's
synchronous chips. For most
applications, manufacturers have found ways to make
synchronous chips that are fast enough
without hogging too much
power.
Also, most semiconductor companies employ
those that have
been working in synchronous designs for
years. You can expect
that they'd want to protect their vested
interests, at least until
they've found a way to compete with or
subsume the younger
firm.
But as the world leans toward computing with portable,
Net-connected devices, asynchronous designs
could win big, or at
least become an interesting alternative in
the future. Of course,
this speculation depends on what will happen
when ADD makes
Vortex commercially available sometime next year.
Discuss today's Lab Rat column in the Labrat
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