WWDTM for today round one

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From: Tom Whore (tomwhore@inetarena.com)
Date: Fri Oct 20 2000 - 08:58:16 PDT

Its the most capable superscalar RISC core yet seen,
the design implemented in a state of the art 0.18 um SOI CMOS
process utilizing 7 layers of copper interconnect. Not satisfied with
that it has not one but two processor cores on a huge 400 mm2 die with three
independent, high bandwidth L2 caches, each approximately half a megabyte
in capacity. In addition, this device integrates controller logic
for external L3 cache and main memory, along with interprocessor
communications channels for a total chip complexity of about 170 million

What is it.

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