RE: Handel-C (compile to wire, not code)

Date view Thread view Subject view Author view

From: Eugene Leitl (
Date: Thu Oct 05 2000 - 02:59:25 PDT writes:
> PS No follow ups - does nobody but me get excited by hardware any more?? :-(

Cute. As you surely know, FPGAs are currently being considered for HF
DSP and crypto. Eventually we'll see FPGA areas in CPU cores, which
should have excellent synergy with embedded DRAM and ultra-wide
buses. (Btw, I can send you a 16 bit MISC Forth CPU in a few lines of
VHDL, which will run in an off-shelf FPGA). It is really nice to be
able to modify the structure of the CPU itself in realtime with a
bitpattern residing on-die, accessible via a >1 kBit
bus. Self-modifying code^2, yummy. Analog FPGAs are also being
considered the killer substrate for evolvable hardware (EHW, see Moshe
Sipper, Hugo de Garis et al.)

However, on the long term this will be obsoletified by cellular
automata hardware (see also crystalline computation,
computronium). Here are a few quick arguments why:

* the larger the die, the higher the percentile of a wafer's silicon
  real estate taken out by a random defect hit during production.
  taken to the extreme, this spells out tiny primitive cells only
  connected to their local neighbours

* as structures grow smaller, defect rate arising during operation due to
  electromigration and Co will go up sufficiently to require adaptive,
  self-healing hardware.
  this spells a redundant array of primitive (to reduce the
  degradation quanta of the incrementally failing system) cells

* as switching speed goes up, relativistic latency will start
  constaining on-die accesses to immediate vicinity

* active signal propagation knows no fanout problems nor signal
  degradation (see biology)

* self-assembled molecular circuitry can only sustain extremely
  primitive computational cells, assembled in 2d and 3d arrays.
  we need 2d molecular circuitry to keep Moore log plot linear
  beyond 2014.

* "Ultimate theoretical models of nanocomputers", Nanotechnology 9
  (1998) pp. 162-176. Can find it on the web, probably at

* I would probably add to this reversible logic (the total number of
  ones and zeros stays the same during system evolution) and EoC (edge
  of chaos) rule requirements.
  however, while former points are still compatible with silicon compiler
  paradigm (albeit expanded to 3d), the latter point blows current software
  development/paradigm totally out of the water, blurring the
  differences between hardware, code, and data, turning everying
  into hyperactive bit soup.
(Sorry if I've weirded out anybody, but above gibberish actually makes
sense, even without a killer hit of acid. It's terribly hard to
predict when above hardware will hit the streets, though. Whoever is
going to try to push above with a startup before its time will
certainly crash and burn horribly, even if backed up with many
billions of VC $$$s).

Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Oct 05 2000 - 04:07:58 PDT