[FoRK] 64-core mesh from Tilera

Steve Nordquist <saigua at sbcglobal.net> on Mon Aug 20 20:08:17 PDT 2007

Kate Green in MIT Technology Review >The new chip, called Tile64, avoids some of the speed bottlenecks inherent in today's chip architecture, and it can operate at much lower power, says Anant Agarwal, founder and chief technology officer of Tilera, based in Santa Clara, CA. Initially, Tile64 will be used in video applications such as videoconferencing systems, and in network hardware that monitors traffic to reduce e-mail spam and viruses.

Videoconferencing spam?  So how do I 'reach out and flightcheck someone' making lots of lousy 11k pdf attachments?  How about just an arm bar?  (Tune in for another exciting Oprah as she clocks the kid who sent us all drug ads from her magnet school....  Simulcast with Barbara Walters failing to understand 5 angles of the pump-and-dump, only on PbyP on 2chan.)

The website showing a BGA 2400 or something; and can their demo board (or the same chip) have DDR2 drivers onboard? http://tilera.com/company/about_us.php
The conscientious first-comer will presumably shim water cooling blocks in with this PCIe 1x board or spec a chiller to meter test applications?
Time was, boiling oil and 64-core hotswap units were considered overkill.  But since it's expected to embed graphics (3d and the ever-hungrier font engine) pipelines, no more.  The minimum 256-bit wide RAM interface ought to give that wife and kids a better time of test-driving too.

> Agarwal explains that Tilera's chip has no central bus. Instead, each core is connected to all the others.

...he would later change from the gravity-based interconnect to kethernions when 802.11fy interference created atonal ringing noise in that field.

>Tilera's Agarwal says that his company has addressed that concern by providing a software environment that helps customers gradually upgrade, debug, and optimize their applications to work on the 64-core system--even applications designed to run on a single core.

What in the world is making people say that the MP cases are intractable to programmers and other designers, never minding that Anant A. has done a chunk of the contrary kernel examples? (kthx.)  

>The company's technology is being presented this week at the Hot Chips symposium at Stanford, in Palo Alto.

Hot interconnect too!  .2-micron 100-mil (and longer) interconnect with .4-ohm resistance?!  My poor fingers!

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