[FoRK] The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit

Eugen Leitl eugen at leitl.org
Tue Sep 6 06:12:56 PDT 2011


(please, please MRAM, don't pull a magnetic bubble on us)

http://low-powerdesign.com/sleibson/2011/09/04/the-return-of-magnetic-memory-a-review-of-the-mram-panel-at-the-flash-memory-summit/

The return of magnetic memory? A review of the MRAM panel at the Flash Memory
Summit

Posted on September 4, 2011 by sleibson321

Prior to 1970, magnetic memory in the form of little ferrite cores dominated
the computing landscape. According to Wikipedia, the first core memory was
installed in the groundbreaking MIT Whirlwind computer in 1953. (Note: I have
a copy of the Encyclopedia Brittanica Yearbook for 1953 that mentions the
development of magnetic-core memory by RCA.) That first core memory installed
into Whirlwind held 1024 16-bit words, so it was a 2-Kbyte memory. For the
next 30 years, computers used core memory for fast data and instruction
storage almost exclusively. Mainframes used it. Minicomputers used it. Even
HP’s first desktop calculator, the HP 9100 introduced in 1968, used a
2208-bit lithium-ferrite core memory to store numbers in its three working
registers. Intel’s introduction of practical, commercial semiconductor memory
in 1970—the famous and infamous 1103 DRAM—completely altered the landscape
because efforts to automate the manufacture of core memory always met with
failure. They always had to be hand-threaded while semiconductor memory—once
debugged—enjoyed the immense advantages of lithographic mass production.
Semiconductor memory in the form of DRAM, SRAM, EPROM, EEPROM, and Flash
memory has dominated the digital world for the last 40 years.

Wikipedia also says that the age of magnetic memory ended in 1975. But
perhaps magnetic memory didn’t die in 1975. Perhaps it was just sleeping.
That could easily have been the theme of the panel on MRAM (magnetic RAM)
that took place at the Flash Memory Summit, held at the Santa Clara
Convention Center last month, which featured representatives from several
companies developing MRAMs including Avalanche Technology, Crocus Technology,
Everspin Technologies, and newcomer Spin-Transfer Technologies LLC.

The panel opened with some remarks from moderator Alan Niebel of Web-Feet
Research, who noted that research on MRAM started 30 years ago with early
experiments on GMR (giant magnetoresistive) MRAM cells and on magnetic tunnel
junction (MTJ) MRAM cells. Motorola Semiconductor was an early pioneer in
developing MRAM and its work passed through to the semiconductor spinoff now
called Freescale, which further spun off the MRAM efforts to Everspin in
2008. Note, I’m pretty sure that “Everspin” is supposed to refer to the
magnetic moment caused by spinning electrons that makes MRAM (and all other
magnetic devices) work and not to the apparent desire to constantly spin off
the MRAM technology to another company.

Increasingly, said Niebel, the interest in MRAM is centering around the
latest and greatest incarnation of the MRAM cell, called STT (spin-torque
transfer), which promises low-power operation and smaller cells that could
lead to immense density improvements. Currently, Everspin’s devices are in
the Mbit density range. STT cells will bump that density to Gbits.

The first panelist to speak was Dr. Rajiv Ranjan, CTO and founder of
Avalanche Technology—founded in 2006. He started his talk by saying that the
materials science behind MRAM technology is well understood because it’s the
same magnetic material used in hard drives. In fact, said Ranjan, storage
built from MRAM could be viewed as “hard drives that don’t spin
[mechanically].” The physics of this magnetic material was all published 20
years ago and that material has no wearout-failure mechanisms. Consequently,
MRAM cells have essentially infinite endurance in contrast to other competing
nonvolatile-memory technologies such as NAND Flash memory or phase-change
memory.

Ranjan noted some important gating factors for MRAM to become successful.
First, it must be compatible with CMOS logic because that’s the process
driver for the underlying circuitry that will drive the MRAM cells. Second,
the MRAM cells must therefore have switching voltages on the order of 0.5V.
Currently, the company has MRAM cells working at the size of 15 F-squared
(the area measurement favored by semiconductor memory makers) and that the
company is shooting for 8 F-squared for its ultimate cell design.

The next panelist to speak was Barry Hoberman, Chief Marketing Officer of
Crocus Technology. Hoberman said that Crocus has developed a “Magnetic Logic
Unit” (MLU) architecture that can be used to implement MRAM cells or pulsed
logic circuits (as opposed to the non-pulsed logic gates generally in use
today). The MLU cell architecture could be used for CAM, secure memory,
pattern matching, and look-up tables said Hoberman.

He then started to discuss the stability of the magnetic material used for
MRAMs. You need to make the material “soft” enough so that you can write the
cell but not so soft that it can be changed by external factors. With
conventional MRAM, said Hoberman, “you lose stability as you scale.” Crocus
currently uses a thermally assisted switching (TAS) mechanism for its MTJ
cells, which decouples scaling from stability. Each cell has a heater that
makes the cell softer magnetically during a write.

Steffen Hellmold, VP of marketing at Everspin, chose to emphasize Everspin’s
early entrance into the MRAM market. He said that Everspin currently offers
the only commercial MRAM parts to date. Everspin has shipped 3 million
devices to more than 300 active customers so far and expects to ship another
300 million pieces during 2011. The company currently offers more than 70
different part numbers in x8, x16, and serial I/O configurations.

Hellmold echoed Ranjan’s earlier assertion that MRAM doesn’t offer
“virtually” unlimited read/write endurance, it offers genuinely unlimited
endurance. Further, he said, MRAM offers instant on/off capability. System
shutdown can therefore be immediate. There’s effectively no latency involved
with the final write during a shutdown because the write cycle for an MRAM
cell is on the order of nanoseconds not milliseconds as it is for NAND Flash.
In addition, there’s no boot time required during power-up because MRAM used
as the local RAM saves the state of the system in place when powered down.
Finally, Hellmold predicted that Everspin would be the first company to
commercialize STT MRAM.

Steve Cliadakis, the General Manager of newcomer Spin Transfer Technologies,
didn’t have much to say at the panel because his company is quite new. Like
the other companies mentioned above, Spin Transfer Technologies working on
spin-torque-transfer MRAM because of the small cell size and small write
currents. The “twist” in Spin Transfer Technologies’ work is that it is
developing a specially aligned magnetic layer that is polarized orthogonally
to the write current through the MRAM cell. When questioned, he said this was
a matter of changing the way the electrons were spin-polarized as they pass
through the polarization layers that form part of any STT MRAM cell. Spin
Transfer Technologies believes that this differentiating technology will
permit the development of even smaller, faster MRAM cells that require even
less write current. In experiments, the company has seen individual MRAM
cells that switch in 100 psec and 99% of the cells created in early
experiments switch in less than 1 nsec. Also, said Cliadakis, the company
believes that sub-100-psec devices should be feasible.

This entry was posted in MRAM and tagged Avalanche Technology, Crocus
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