[FoRK] Fwd: Sandia Lab Fires Up 300, 000 Virtual Android Devices To Test Out Security
sdw at lig.net
Wed Oct 3 09:30:44 PDT 2012
On 10/3/12 7:30 AM, Joseph S. Barrera III wrote:
> On 10/3/2012 12:09 AM, Stephen Williams wrote:
> > It also means that it runs full speed: no instruction set emulation of ARM.
> > The latter is tough because in a lot of ways, ARM has better instructions than X86,
> > even if they don't execute as fast overall.
> Oh, right, the classic RISC/CISC tradeoff. ... wait, what?
Pentium-class effectively became RISC several cycles ago which is why simple RISC faded, IMHO. ARM seems more CISC than RISC,
which probably why it is slower. Also, I don't think that ARM does the CISC->RISC instruction decoding, intensive register
renaming, deep instruction level parallelism, extreme branch prediction, and multi-path execution that Pentium-class does. Plus
cache sizes need to be larger. Too much wasted power for mobile.
More cores running slower can be as fast at much lower power. (That's a design law that's generally true.) Expect 8-16-core
CPUs in the near future.
> - Joe :-)
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