[FoRK] advances in spintronics

Gregory Alan Bolcer greg at bolcer.org
Fri Nov 23 07:56:18 PST 2012

Good for laptops, bad for workstations.

Although I wonder if you couldn't use 6 slots for 8 or 16GB per slot 
traditional DDR3 and the remaining two for 2GB of "power persistent" 

I wonder if the design deprecates ECC? Or do you still need to do ECC 


On 11/23/2012 7:05 AM, Eugen Leitl wrote:
> http://semiaccurate.com/2012/11/16/everspin-makes-st-mram-a-reality/
> Everspin makes ST-MRAM a reality
> LSI AIS 2012: Non-volatile memory with DDR3 speeds
> Nov 16, 2012 in Storage
> by Charlie Demerjian
> logo everspin 63x17 Everspin makes ST MRAM a realityEverspin has introduced a
> production ST-MRAM memory that combines high speeds, high density, and
> non-volatile storage. Best of all, it can be produced on normal semiconductor
> lines at bleeding edge geometries.
> MRAM is short for Magnetoresistive RAM, and up until this anouncement was
> only available in Toggle form. Now Everspin has announced ST-MRAM or Spin
> Torque MRAM, and sample boards are available now. ST-MRAM takes less power to
> switch, to run, and the cells can shrink with smaller processes just like
> transistors.
> The ST-MRAM shown today is built on a standard 90nm process, and from that
> you get a 64Mb chip that is pin compatible with a DDR3 DRAM. That means for a
> comparable size device, you can get the DIMM pictured below but it doesn’t
> lose data when powered off. Densities start off at 64MB, remember this is a
> 90nm product, and the speeds are comparable to current DDR3/1600MHz.
> Everspin ST MRAM DIMM Everspin makes ST MRAM a reality
> 64MB Everspin ST-MRAM in DDR3 DIMM format
> Timings are also comparable to DDR3/1600, but not exactly the same. This
> isn’t marketing-speak to hide a flaw, the CAS latency is the same, but the
> other timings are different due to how MRAM works.  This means higher access
> granularity and no needed refresh, so accesses can be done quite differently.
> Since ST-MRAM does not need to be refreshed, that changes how bits can be
> accessed and patterns are optimal to read it with. All of the old DRAM tricks
> for banks, accesses, and block reads are not necessarily beneficial for this
> technology, and that changes just about everything. This is not to say it is
> worse, more granular and faster without refresh related rules is a very good
> thing.
> Current DDR3 controllers, if they follow the spec fully, should be able to
> work with ST-MRAM. They will undoubtedly need a firmware update to make them
> aware of the non-volatile nature of the memory, but that is understandable.
> These updates should also let you do a lot more tricks with access, the old
> handcuffs are not there any more. The short story is that with very little
> work, it should work with many modern memory controllers.
> Looking forward a bit, if you can get 64Mb chips out of a 90nm process, think
> about what happens when you move to a modern process. Process steps are 90nm,
> 65nm, 45nm, 32nm, and now down to 22nm. That means the 64Mb parts are built
> on a -4 process, or to put it another way, would get 16x the density moving
> to a bleeding edge process. I will let you do the math, but a 20/22nm MRAM
> will hold a bit less than current DRAMs on the same process and not lose it
> when you pull the plug. Everspin assures SemiAccurate that it does shrink to
> those geometries and that dies sizes are roughly the same as DRAM for the
> same capacity chip.
> Better yet, switching a bit cell is determined by current density, so energy
> used goes down with the square of the process size, but not exactly. There
> are a few other factors to take in to account, but each shrink should bring a
> large power savings with it like you might typically expect from
> semiconductors. Normal DRAMs don’t shrink nearly as well, and flash is at the
> point of decreasing performance as process get smaller too.
> Everspin ST MRAM in LSI card Everspin makes ST MRAM a reality
> ST-MRAM working in an LSI RAID card
> Everspin is saying that the pricing of MRAMs now is comparable to SRAMs, that
> would be very high to you and me. With the advent of ST-MRAM, when volume
> goes up prices should drop to that of standard DRAMs. For non-volatile memory
> that is in the ballpark of current alternatives for energy use all while on a
> 90nm process. Impending shrinks mean ST-MRAM has a pretty good outlook. Once
> this technology goes mainstream it will change things, count on it.S|A
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greg at bolcer.org, http://bolcer.org, c: +1.714.928.5476

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